Lieu : Villeneuve Loubet (06) · Contrat : Stage · Rémunération : A négocier
Codasip develops a portfolio of RISC-V based processors, easily customizable using a
unique toolset, Codasip Studio. We are hiring in the newly created design center opened
in Villeneuve-Loubet city in the south of France.
Do you want to work on the leading edge of a diverse range of technologies, shaping a new era of processing technology? Be a part of a skilled and friendly team based in the heart of Europe? Codasip may be just what you are looking for.
CHALLENGE TO TACKLE
Codasip develops test benches to verify parts of the CPU (like integer core, L1 caches, ALU, etc…). These test benches use random generators to produce flow of pseudo instructions to exercise the RTL code. One of these generators is developed by the Sophia team and aims at disclosing new categories of bugs in the cache memories. The current version is limited to only block level test benches. What about extending it to make it platform agnostic so that it can be used in bare metal, in simulation or even on FPGA prototypes?
At the end of the internship, you will have:
• Coded in python the main assembly-generation engine of the tool
• Handled a simple model of a CPU to predict results
• Produced self-checking mechanisms and algorithms
• Hopefully found new bugs in our RISC-V CPUs under development.
Philippe LUC will be your mentor. He will help you feel integrated in the team as an engineer and guide you during the internship. Feel free to contact him at firstname.lastname@example.org for further question.
• Software writing skills (preferably python)
• Knowledge of CPU microarchitecture
• Knowledge of compilation and cross compilation flow
• Knowledge of Version Control System (Git)
• Spoken and written English is a must
• Active interest in the field and self-education